LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.components.fulladder;

ENTITY ula IS
	PORT( Op				: IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
		  X, Y				: IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
		  S					: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		  Cout				: OUT STD_LOGIC;
		  Overflow			: OUT STD_LOGIC);
END ula;

ARCHITECTURE Behavior OF ula IS
	SIGNAL Cin 		: STD_LOGIC;
	SIGNAL C 		: STD_LOGIC_VECTOR(1 TO 8);
	SIGNAL addSub 	: STD_LOGIC_VECTOR(7 DOWNTO 0);
	
BEGIN
	Cin <= Op(0);
	stage0: fulladder PORT MAP (Cin, X(0), Y(0) XOR Cin, addSub(0), C(1));
	stage1: fulladder PORT MAP (C(1), X(1), Y(1) XOR Cin, addSub(1), C(2));
	stage2: fulladder PORT MAP (C(2), X(2), Y(2) XOR Cin, addSub(2), C(3));
	stage3: fulladder PORT MAP (C(3), X(3), Y(3) XOR Cin, addSub(3), C(4));
	stage4: fulladder PORT MAP (C(4), X(4), Y(4) XOR Cin, addSub(4), C(5));
	stage5: fulladder PORT MAP (C(5), X(5), Y(5) XOR Cin, addSub(5), C(6));
	stage6: fulladder PORT MAP (C(6), X(6), Y(6) XOR Cin, addSub(6), C(7));
	stage7: fulladder PORT MAP (C(7), X(7), Y(7) XOR Cin, addSub(7), C(8));
	Cout <= C(8) AND Op(1);
	Overflow <= (C(8) XOR C(7)) AND Op(1);
	
	-- "00" - AND 
	-- "01" - OR
	-- "10" - ADD
	-- "11" - SUB
	WITH Op SELECT 
		S	<=	(X AND Y) WHEN "00",
				(X OR Y) WHEN "01",
				addSub WHEN OTHERS;
				
END Behavior;